NBTI aging analysis and aging-tolerant design of p-type domino AND gatesp

NBTI-induced PMOS transistor aging has become a prominent reliability concern in the nano-scaled IC design. In this paper, the impact of NBTI on the main performances of P-type domino AND gates which are used widely for designing high performance digital integrated circuits, is analyzed by HSPICE simulation. Experimental results show that under 110 degree centigrade, the time delay of the 32nm technology P-type domino AND gate affected by NBTI aging for a decade, increases up to 11.450%, potentially leading to functional failure. Considering the difference of the impact of different part of PMOS transistors NBTI aging on AND gate performance, a new P-type domino AND gate is proposed with multi-threshold voltage PMOS transistors configuration scheme introduced. Compared with the existing P-type domino AND gate, the proposed AND gate can provide 10.397% timing margin for circuit aging with same noise margin and 0.916% power consumption reduced, so that the lifetime of domino circuit is guaranteed.