Nanomagnetic Logic Microprocessor: Hierarchical Power Model

The interest in emerging nanotechnologies has been recently focused on nanomagnetic logic (NML), which has unique appealing features. NML circuits have very low power consumption and, because of their magnetic nature, maintain the information safely stored even without power supply. The nature of these circuits is much different from that of CMOS circuits. As a consequence, to better understand NML logic, complex circuits and not only simple gates must be designed. This constraint calls for a new design and simulation methodology. It should efficiently encompass manifold properties: 1) being based on commonly used hardware description language (HDL) in order to easily manage complexity and hierarchy; 2) maintaining a clear link with physical characteristics; and 3) modeling performance aspects such as speed and power, together with logic behavior. In this paper, we present a very-high-speed integrated circuits HDL (VHDL) behavioral model for NML circuits, which allows the evaluation of not only the logic behavior but also its power dissipation. It is based on a technological solution called “snake-clock.” We demonstrate this model using a case study which offers the right variety of internal substructures to test the method: a 4-bit microprocessor designed using asynchronous logic. The model enables a hierarchical bottom-up evaluation of the processor logic behavior, area, and power dissipation, which we evaluate using a benchmark division algorithm. The results highlight the flexibility and the efficiency of this model, as well as the remarkable improvements that it brings to the analysis of NML circuits.