Criteria to minimize power consumption of frequency domain equalizers in VLSI implementations

Nowadays in optical communications, equalizers to compensate chromatic dispersion have a large impulse response and throughput, therefore the VLSI implementation of this filters are carried out in frequency domain to reduce its complexity and thus achieve a lower power consumption. Designers facing developments of frequency domain filters have defined in advance the throughput and the impulse response of the filter, but the FFT/IFFT size and its implementation architecture are design variables. This work proposes general criteria for selecting these parameters to reduce filter power consumption.