CMOS LNA using 130nm process with improved Noise Figure and linearity using Harmonic rejection technique

A Cascode differential LNA using 130nm CMOS process is proposed. The linearity enhancement is achieved by, restrained generation of 3rd order Harmonic component. To cancel the 3rd Harmonic component, a RC feedback from Drain node of common-gate to the Source node of common-gate transistor is used. To achieve low Noise Figure, Cascode stage transistors are used. This technique is verified by comparing the design of Classical LNA and the Proposed LNA. The LNA achieves Noise Figure 2.435dB, Input-referred P1dB -4.18dBm and Gain 19dB. From these measured result the Proposed LNA successfully proves that it has minimum Noise Figure and is linear.