Efficient hardware multiplier design for pairing computation

In Public Key Cryptography, the most costly arithmetic operation is first inversion then multiplication. There aren´t big researches concerning modular inversion, it exist two famous algorithms which are Fermat and Extended Euclid algorithms. All researches are oriented to the modular multiplier, it exist a big number of methods to compute it. The goal of our paper is to present a of a 256-bits multiplier design, to compute pairings at security level of 128-bits. Our hardware architecture exploits FPGA features (Fast Carry Chain and DSP), for this reason, it´s less constrained in memory and power consumption. These performances prove the limitations of the restrained environment. Our design is coded in VHDL language and synthesized using Xilinx ISE 14.5 on Virtex 6 FPGA XC6VLX240T devices. Our multiplier used only 1665 slices and 3 DSP, it runs at 149.8 MHz clock frequency.