Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders

Multi-operand addition is found in many real-life applications. In this paper, we propose two approaches for realizing multi-operand addition using two-operand adders on Field Programmed Gate Arrays (FPGAs). The proposed approaches reduce the area of the final implementation while reducing its propagation delay. We focus on the case where the operands are of different sizes.