Robust FinFET based highly noise immune power gated SRAM circuit design

Leakage power dissipation, timing delay and high noise immunity in advanced embedded static random access memories cells are main critical issues in low power battery operated devices. The newly proposed FinFET based highly noise immune Power gated 6T SRAM design is targeting these areas and successfully suppress leakage power dissipation with maintaining stability of data in standby mode. A single ended read and write assist circuitry is also presented to here, which enhancing read and write noise margin for maintaining robustness of SRAM stability. As compared with conventional FinFET SRAM designs in the proposed design, the power dissipation in SLEEP mode is reduced up to 86.8% and, read and write power consumption are up to 98.9% and 16.5%, respectively. The noise margin of proposed design is increased up to 45× as compared to self-reverse biased power gated SRAM at 32nm technology node.