DocumentCode
3779701
Title
Fllckcr noise in CMOS: A unlfied model for VLSI processes
Author
A. A. Abidi;C. R. Viswanathan;J. J.-M. Wu;J. A. Wikstrom
Author_Institution
Integrated Circuits & Systems Laboratory, Electrical Engineering Department, University of California, Los Angeles, CA 90024
fYear
1987
fDate
5/1/1987 12:00:00 AM
Firstpage
85
Lastpage
86
Abstract
An experimental study of flicker noise in CMOS devices, obtained from three different, production level, fabrication lines, indicates that the noise characteristics of the devices do not vary significantly amongst fabricators, or depend on the doping type of the CMOS well. Noise in NMOS may be modelled in all regions of device operation by a single measured parameter. This supports the carrier density fluctuation model of flicker noise. In equal sized PMOS devices, the equivalent input noise power may be smaller by up to two orders of magnitude. An increasing noise with VGS indicates an energy dependence of density of those oxide traps that are responsible for hole trapping.
Keywords
"Logic gates","Semiconductor device modeling","1f noise","CMOS integrated circuits","Fabrication","MOSFET"
Publisher
ieee
Conference_Titel
VLSI Technology, 1987. SymVLSITech 1987. Symposium on
Print_ISBN
978-1-5090-3151-1
Type
conf
Filename
7508728
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