• DocumentCode
    3779715
  • Title

    Submicron gap planarization with photo CVD and spin-on-glass multi-layers for multi-level interconnections

  • Author

    K. Yano;S. Tanimura;T. Ueda;T. Fujita

  • Author_Institution
    Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd., Moriguchi, Osaka, Japan
  • fYear
    1987
  • fDate
    5/1/1987 12:00:00 AM
  • Firstpage
    71
  • Lastpage
    72
  • Abstract
    The planarization process utilizing Photo CVD and SOG multi-layers has been developed to bury 0.6 μm gaps (aspect ratio 1.33). The insulator film was successfully refilled in submicron gaps regardless of tapered angle and sidewall morphology. This technology is applied to multilevel metallization, and provides excellent planarization characteristics and electric characteristics.
  • Keywords
    "Planarization","Temperature measurement","Substrates","Leakage currents","Films","Scanning electron microscopy","Dielectrics"
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 1987. SymVLSITech 1987. Symposium on
  • Print_ISBN
    978-1-5090-3151-1
  • Type

    conf

  • Filename
    7508741
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3779715