DocumentCode
3779727
Title
PASPAC (Planaraized Al/Silicide/Poly Si with self aligned contact) with low contact resistance and high reliability in CMOS LSIs
Author
Masakazu Kakumu;Tetsuya Asami;Kazuhiko Hashimoto;Jun´ichi Hatsunaga
Author_Institution
Semiconductor Device Enginnering Laboratory, TOSHIBA Corporation, 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki 210, Japan
fYear
1987
fDate
5/1/1987 12:00:00 AM
Firstpage
77
Lastpage
78
Abstract
PASPAC system has been proposed. Using this technology, planarization at the contact area has been accomplished, which gives a large impact on multi-level interconnection process. Moreover, low resistive and thermally stable ohmic contact can be obtained even at submicron region. In this structure, contact characteristics are readily controlled by implanted ion dose, which also acts as self aligned contact. This technology, combined with an advanced CMOS process appears to be a quite promising metallization system for submicron CMOS LSI´s in view of low resistive self aligned contact and high reliable interconnection.
Keywords
"Silicon","Contact resistance","Reliability","CMOS integrated circuits","Metallization","Silicides","Junctions"
Publisher
ieee
Conference_Titel
VLSI Technology, 1987. SymVLSITech 1987. Symposium on
Print_ISBN
978-1-5090-3151-1
Type
conf
Filename
7508753
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