• DocumentCode
    3779735
  • Title

    0.5μm CMOS technology for 5.6nsec high speed 16×16 bit multiplier

  • Author

    Kazushi Tsuda;Hiroshi Takato;Maoko Takbnouchi;Kenji Tsuckiya;Yukihito Oowaki;Kenji Numata;Akihiro Nitayama

  • Author_Institution
    VLSI Research Center, TOSHIBA Corporation, 1, Kornukai Toshiba-cho, Saiwai-ku, Kawasaki 210, Japan
  • fYear
    1987
  • fDate
    5/1/1987 12:00:00 AM
  • Firstpage
    109
  • Lastpage
    110
  • Abstract
    CMOS technology becomes indispensable for designing VLSI circuits because of high speed, wide noise margin, and low power dissipation. Moreover, scaled down half a micron CMOS circuits have a large impact on high speed operation, where the speed is comparable to that of bipolar and GaAs. However, when CMOS devices are scaled down to half micron, it is difficult to suppress punchthrough and parasitic resistance for PMQSFETs and hot carrier degradation for NMOSFETs.
  • Keywords
    "Logic gates","Resistance","MOSFET","CMOS integrated circuits","Gallium arsenide","Capacitance","Reliability"
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 1987. SymVLSITech 1987. Symposium on
  • Print_ISBN
    978-1-5090-3151-1
  • Type

    conf

  • Filename
    7508760