• DocumentCode
    3779751
  • Title

    Soft-error immune switched-load-resistor memory cell

  • Author

    Noriyuki Homma;Tohru Nakamura;Tetsuya Hayashida;Motoaki Matsumoto;Kazuo Nakazato;Takahiro Onai;Youichi Tamaki;Mitsuo Namba;Kazuhiko Sagara;Kiyoji Ikeda

  • Author_Institution
    Central Research Laboratory, Hitachi Ltd. KoKubunji. Tokyo 185
  • fYear
    1987
  • fDate
    5/1/1987 12:00:00 AM
  • Firstpage
    37
  • Lastpage
    38
  • Abstract
    Various memory cell sizes that can be obtained with anticipated device size reduction are compared in Fig. 9. It is clear that a future ultra-high-speed high density bipolar RAM with sufficient soft-error immunity is possible using the new memory cell.
  • Keywords
    "Random access memory","Capacitance","Transistors","Switches","Silicon","Substrates","Memory management"
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 1987. SymVLSITech 1987. Symposium on
  • Print_ISBN
    978-1-5090-3151-1
  • Type

    conf

  • Filename
    7508776
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3779751