Title :
Nanoscale register file circuit design — Challenges and opportunities
Author :
Khawar Sarfraz;Mansun Chan
Author_Institution :
Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong
Abstract :
This paper discusses key circuit-level challenges associated with the design of multi-port register file (RF) memories. Notable solutions proposed to address these challenges are presented. Some of the challenges and opportunities associated with novel device structures at advanced process nodes are covered together with interconnect scaling issues, advancements in and expectations from CAD tools, and layout concerns.
Keywords :
"Radio frequency","Logic gates","Power demand","Transistors","Delays","Robustness","Clocks"
Conference_Titel :
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN :
978-1-4799-8483-1
Electronic_ISBN :
2162-755X
DOI :
10.1109/ASICON.2015.7516882
