A low voltage SRAM sense amplifier with offset cancelling using digitized multiple body biasing

An offset cancelling technique with digitized multiple body biasing (DMBB) has been proposed. In this scheme, transistors threshold voltage mismatch in latch type sense amplifier (SA) is compensated by adjusting the body bias voltage digitally and repeatedly. Simulated results in 130-nm CMOS technology show that the proposed calibration technique can reduce the standard deviation of offset voltage by over 4X comparing to conventional sense amplifier. In addition, this calibration technique only introduces a little area overhead and some calibration clocks.