DocumentCode :
3781161
Title :
A load-transient-enhanced output-capacitor-free low-dropout regulator based on an ultra-fast push-pull amplifier
Author :
Shaowei Zhen;Ji Wang;Dongjie Yang;Canhua Cao;Ping Luo
Author_Institution :
State Key Laboratory of Electronic Thin Films and Integrated Devices
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
The paper proposed an ultra fast response output capacitor free (OCF) low dropout regulator (LDR) based on an ultra fast push-pull error amplifier. The amplifier detects the output voltage spike (the overshoot or undershoot voltage) of the LDR and generates an ultra-fast and large adaptive current to push up or pull down the gate of the power transistor to enhance the load transient performance. Based on quadratic I-V characteristics of MOS transistor, and adaptive biasing, the slew rate (SR) of amplifier in LDR is enhanced. The output driving capability is further improved by slew rate enhanced charging/discharging circuit. As a result, the amplifier performs transfer characteristics of much higher current capability and the output current is no longer limited by tail current or square-law in conventional designs. Designed in a 0.35μm CMOS process, the LDR is stable for 0pF to 50pF load capacitance and has 100mA maximum load capability with a quiescent current of 14μA. Simulation results including all process corners show that the undershoot/overshoot voltage are reduced to 147mV/57mV for load step from 1mA to 100mA in 100ns, and the recover time is only 210ns in worse case.
Keywords :
"Mirrors","Transient analysis","Logic gates","Transistors","Capacitors","Transient response","Gain"
Publisher :
ieee
Conference_Titel :
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN :
978-1-4799-8483-1
Electronic_ISBN :
2162-755X
Type :
conf
DOI :
10.1109/ASICON.2015.7516898
Filename :
7516898
Link To Document :
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