DocumentCode :
3781186
Title :
Ultra-short length stochastic computation based on multiple partition computing
Author :
Jienan Chen;Jianhao Hu;Jiangyun Zhou
Author_Institution :
University of Electronic Science and Technology of China, Chengdu 611731, China
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
In this paper, we propose an ultra-short length stochastic computation (SC) method based on multiple partition computing (MPC). For example, in MPC four parallel 16-bits streams can represent a 16-bits fixed-point number, while a 65536-bits stream is required in traditional SC. To achieve this, MPC partitions a fixed-point number to several short parts and converts each part to a short stream separately. A high performance stochastic multiplier and a divider are also proposed based on MPC. As a case study, we implement a 4×4 matrix multiplication with field programmable gate array (FPGA). The synthesis reports shows that the hardware efficiency of the proposed method is 76X times more than traditional SC and 23% improvement than the traditional fixed-point computation.
Keywords :
"Hardware","Field programmable gate arrays","Logic gates","Computational efficiency","Signal representation","Signal to noise ratio"
Publisher :
ieee
Conference_Titel :
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN :
978-1-4799-8483-1
Electronic_ISBN :
2162-755X
Type :
conf
DOI :
10.1109/ASICON.2015.7516930
Filename :
7516930
Link To Document :
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