A novel power optimization mechanism for pipelined ADCs

This paper presents a novel power optimization mechanism for pipelined ADCs to release the design limitation by stage partition and the ratio of MDAC´s OTA power to sub-ADC´s comparator power. According to the theoretical analysis and simulations, for ADCs where power consumption and thermal noise dominate, the optimized design scheme is that each stage resolves 2 bits and has a scaling factor of 1/3. A 10-bit pipelined ADC fabricated in TSMC 90nm CMOS technology has been designed to verify the power optimization mechanism.