A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC

In this paper, a high speed analog front-end circuit used in a 12bit 1GSps pipeline ADC is presented, the circuit is composed of a high speed on-chip input buffer and a flip-around sample-and-hold (S/H) amplifier, by using N-well Electric potential bootstrapping technique, the circuit acquired a excellent performance at high input frequency. The entire circuit was designed in TSMC 65nm CMOS process. Transient simulation without noise shows that when work together with an embedded 12bit 1GSps A/D conversion core, the circuit achieves a SNDR of 81.93dB and a SFDR of 82.42dB with an input frequency of 57.6MHz, and when the input signal frequency increase to 476MHz, the circuit achieves a SNDR of 76.48dB and a SFDR of 76.8dB.