A network components insertion method for 3D application-specific Network-on-Chip

In this paper, we propose a two-phase method to solve the problem of the network component insertion for 3D application-specific Network-on-Chip (NoC). A model based on genetic algorithm is conducted at the first phase, in order to obtain optimal insertion positions of routers and network interfaces with minimal total network interconnection power consumption. Then some routers are merged to further reduce the power consumption and resource costs. Experimental results on several multimedia benchmarks show that, compared to the random insertion method, our method saves about 38.9% of the total network interconnection power consumption on average, and also reduces the resource costs.