Title :
Design and optimization of asynchronous circuits with gate-level pipelining
Author_Institution :
Department of Electric Engineering and Information Systems, the University of Tokyo, Tokyo 113-0032 Japan
Abstract :
We have been working for asynchronous control with fine-grain pipeline circuits, namely, self-synchronous circuits. We have demonstrated self-synchronous FPGA and self-synchronous RSA crypt-engine, to show energy consumption reduction at the energy minimum operating point, by gate-level power gating, and tamper resistivity of crypt-engine by dual-rail asynchronous operations. It is, however, realized by custom design. This paper presents several trials for automated design optimization of the self-synchronous circuits.
Keywords :
"Logic gates","Pipeline processing","Robustness","Cryptography","Power supplies","Timing","Throughput"
Conference_Titel :
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN :
978-1-4799-8483-1
Electronic_ISBN :
2162-755X
DOI :
10.1109/ASICON.2015.7516956
