Electrical Overstress (EOS): Challenges for component and system-level co-design

Electrical Overstress (EOS) continues to impact semiconductor components and systems as technologies scale from micro-to nano-electronics [1-10]. This paper will teach fundamentals of electrical overstress (EOS) and how to minimize and mitigate EOS failures [1]. The paper will provide a clear picture of EOS phenomena, EOS origins, EOS sources, EOS physics, and failure mechanisms. The paper will focus the challenges to achieve robust design for component and system level with co-design of EOS and ESD.