DocumentCode :
3781249
Title :
Fibonacci sequence weighted SAR ADC algorithm and its DAC topology
Author :
Takuya Arafune;Yutaro Kobayashi;Shohei Shibuya;Haruo Kobayashi
Author_Institution :
Division of Electronics and Informatics, Gunma University, 1-5-1 Tenjin-cho Kiryu Gunma 376-8515, Japan
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
This paper describes redundant successive approximation register (SAR) ADC design methods to improve reliability and conversion speed by digital error correction. Especially we show that redundant SAR ADC using Fibonacci sequence and its property called Golden ratio can be well-balanced design. We also present some simple golden-ratio-weighted DAC topologies for easy realization of the redundant SAR ADC by utilizing many interesting properties of Fibonacci sequence.
Keywords :
"Redundancy","Algorithm design and analysis","Error correction","Capacitors","Topology","Resistors"
Publisher :
ieee
Conference_Titel :
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN :
978-1-4799-8483-1
Electronic_ISBN :
2162-755X
Type :
conf
DOI :
10.1109/ASICON.2015.7517012
Filename :
7517012
Link To Document :
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