A lowpass/bandpass reconfigurable continuous-time ΔΣ ADC for software-defined radio

In this paper, a dual-mode reconfigurable lowpass/bandpass continuous-time ΔΣ ADC for software-defined radio is presented. Both system level and circuit level optimization is conducted to minimize the power consumption. A switchable feedforward loop filter with binary OTA unit array is proposed to realize the filter type, noise-shaping order and sampling frequency reconfiguration. A single-bit quantizer and feedback DAC are used to ensure the linearity performance. Simulation results in 90nm CMOS technology show that in the GSM/Bluetooth mode, the 200/500kHz bandpass/lowpass ΔΣ ADC achieves 93/88dB SNR and 93/81.8dB SNDR, consuming 4.7/2.7mW power under 1.2V supply, corresponding to FoM of 321/268fJ/Conv., comparing favorably to other state-of-the-art reconfigurable ΔΣ ADC designs.