An efficient layered ABV methodology for vision system on chip based on heterogeneous parallel processors

The demand of higher performance system on chip (SoC) based on massively parallel processors has increased significantly throughout the last decades. The design verification of the chip becomes one of the major challenges in microelectronics. The paper proposes an efficient Layered Assertion Based Verification (L-ABV) methodology for vision system on chip based on heterogeneous parallel processors. It focuses on the vision SoC pre-silicon verification solutions. First, we discuss on how to reduce the degree of dependency between verification task and design task. Then we split the verification task into different logic layers. L-ABV has been successfully used in Vision SoC to increase the verification productivity. The result shows that it has effectively shortened the verification time.