A PVT variation tolerant and low power 5Gb/s clock and data recovery circuit for PCI-E 2.0/USB 3.0

This paper describes a 5Gb/s CMOS clock and data recovery (CDR) circuit based on phase interpolator and digital filter. It has excellent process, voltage and temperature (PVT) tolerance and low power characteristics. The CDR circuit was fabricated in 65nm CMOS. The actual area is only 0.24mm × 0.33mm. The measured power dissipation was approximately 32mW and jitter performance met PCI Express 2.0/USB3.0 interface and downwards compatible with PCI Express 1.0. Measured results show a 5Gb/s data rate with Bit Error Rate (BER)<; 10-14 across 50cm of PCB.