A method of automatic sizing logic driver of 16nm Fin-FET

In this paper, we study the optimal design of drivers for high performance VLSI system based on the advanced 16nm Fin-FET logic process. The optimal design of drivers is important to the high-speed lower power VLSI, such as the high speed bus of processor, clock network and the critical signals in SOC system. Different from the well known method which optimize the drivers using a fixed size-ratio e(= 2.73) between the neighbor inverters, we optimize sizing drivers efficiently by an automatic method and we will get high performance of inverter chain. Firstly, we derive the relationship among the parameters of delay, driver size (fin numbers), driver stages, input/output (or interconnect) loading. Then, we construct the driver optimal tool based on the parameters´ relationship of the driver.