A novel adaptive CMOS low-dropout regulator with 3A sink/source capability

A novel adaptive CMOS low-dropout regulator (LDO) is proposed for DDR4 memory power supply. By using a two stage structure, this LDO can adjust its transfer path to afford a very large range of load current from 0 A to 3 A. Two NMOS pass elements are used to do both sourcing and sinking functions, which are not included in traditional LDOs. The improved structure with two NMOS transistors performs a good stability by using Miller compensation method. Fast load transition is also obtained due to 20 μF ceramic capacitor at output terminal. The circuit has been demonstrated in TSMC 0.18μm standard CMOS process with a 1.2 V input voltage under 3.3 V supply voltage. The simulation results show that the LDO consumes a quiescent current of 70 μA, the phase margin is at least 47 degree with 1 mA to 3 A load current. The transient output voltage is constrained within 40 mV when load current ramps from 0 A to 3 A with 20 μF capacitor load.