A reference-less all-digital burst-mode CDR with embedded TDC

In this paper, a 1.25 Gpbs all-digital burst-mode clock and data recovery (BM-CDR) circuit with embedded time-to-digital converter (TDC) is presented. The proposed BM-CDR circuit uses an amendatory calculation method to achieve less quantization error. Current-starved inverters with control signals are used to realize fine-TDC to improve the resolution and reduce the power. This circuit is implemented in a 65nm CMOS process. Simulation results show that the clock jitter is reduced from 0.24 UI to 0.027 UI, about 88.75% under 16-bit consecutive identical digits.