An asynchronous delay line TDC for ADPLL in 0.13um CMOS

This paper presents an asynchronous coarse-fine delay line based time to digital converter (TDC) applied to ADPLL. We develop asynchronous coarse-fine delay line architecture to balance measurement and resolution with lower power consumption. Auto control module is developed for switching between coarse and fine line. Phase detectable range is expanded for large frequency error tolerance. Implemented in SMIC 0.13um CMOS, TDC can achieve maximum measurement range of 60ns and minimum resolution of 72ps. Power consumption is 2.86mW (coarse line inactive) and 2.36mW (fine line inactive) on average at 1.2 V voltage supply.