Low voltage adaptive delay clock buffer design

Power consumption becomes issue in circuit design, and low voltage design is a good candidate for low power. However, the timing variation becomes greater when supply voltage scales down to near-threshold resign. The existing methods could not work well at low voltage. We propose a new clock buffer which can get low variation at near-threshold. Our proposal reduces the variation from 139% to 30.3% of 7 level buffer compared to normal buffer, at 0.4V, 32/28nm technology.