Novel CMOS technology compatible nonvolatile on-chip hybrid memory

A hybrid memory is proposed in this paper, it consists of conventional six transistors SRAM cell and nonvolatile part, to reduce static leakage current in sleep mode, in the way that store the value to nonvolatile part, and restore the value to volatile part at the beginning of work mode. It can be used in SOC to store the control words as the whole chip´s power supply is off. The method of operation is presented. Charge pump, sense amplifier, level shifter, pre-charge circuit, and structure are presented to implement the hybrid memory. Monte-carlo simulations are carried out, and the simulation results show that the reliability of restoring to process variation is high enough to ensure hybrid memory work properly. The SNM is same to the conventional 6T SRAM. Compare to conventional 6T SRAM cell, 34.7% write time is cost, read time is same.