Fault detection and redundancy design for TSVs in 3D ICs

Defects in through-silicon vias (TSVs) due to fabrication steps decrease the yield and reliability of 3-D stacked integrated circuits, and hence these defects need to be detected early to reduce chip´s DPM. In this paper, a new fault detection and repair method for TSVs in 3D-ICs is proposed. The contribution of the method is to detect stuck-at-faults and delay-based fault in TSV by a scan-based built-in self-test (BIST) architecture. This test architecture supports both pre-bond and post-bond TSV testing. By constructing RC model and analyzing the delay characteristics of TSV, the variation of TSV-to-substrate resistance caused by TSV defects can be mapped to the change of path delay so that the related fault can be detected. Based on the test architecture, we propose a TSV redundancy structure to repair circuit after failed TSVs are detected. Results of fault detection effectiveness are presented through ModelSim simulations using realistic models under 65 nm CMOS technology. And redundancy design leads to 99.9846% recovery rate for TSVs with only 0.2% redundancy rate of TSVs.