Title :
Analytical models for threshold voltage, drain induced barrier lowering effect of junctionless triple-gate FinFETs
Author :
Guangxi Hu;Shuyan Hu;Jianhua Feng;Ran Liu;Lingli Wang;Lirong Zheng
Author_Institution :
State Key laboratory of ASIC and system, School of Information Science and Technology, Fudan University, 220 Handan Road, Shanghai, China, 200433
Abstract :
Analytical models for threshold voltage, and drain induced barrier lowering effect of the short-channel fin-shaped field-effect transistor (FinFET) are obtained. The analytical model results are verified against simulations, good agreements are observed. The explicit expression for threshold voltage makes the model suitable to be embedded in circuit simulation and design tools.
Keywords :
"Electric potential","Threshold voltage","FinFETs","Simulation","Analytical models","Integrated circuit modeling","Logic gates"
Conference_Titel :
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN :
978-1-4799-8483-1
Electronic_ISBN :
2162-755X
DOI :
10.1109/ASICON.2015.7517154
