A high performance parallel VLSI design of matrix inversion

This paper proposes a high performance matrix inversion hardware implementation which is divided into three steps, namely, LU decomposition, triangular matrix inversion, matrix multiplication. Our proposed design improve the performance of matrix inversion by parallel computing, and ensure the accuracy and stability through pivoting operation in LU decomposition. Experimental results show the speed-up ratio is almost 3 when the matrix order is 144, and the RMS is less than 10^-4. The design can reach a maximum delay of 0.6ns under the TSMC 40nm craft.