Title :
FPGA logic design of SATA3.0 physical layer
Author :
Zong Yang;Hui Xu;Nan Li;Zhaolin Sun
Author_Institution :
Electronic science and engineering, National University of Defense and Technology, Changsha 410073, China
Abstract :
In this paper, we present a SATA physical layer design based on kintex-7 serial FPGAs. This design uses the GTX of the Kintex-7 to interface with SSD devices at SATA 3.0(SATA3.0, 6 Gb/s) speeds and compatible with devices with SATA 2 and SATA 1 speeds. A brief introduction of SATA physical layer protocol is given in the first part of this essay, then we have an quick view of the GTX of Kintex-7 and function block of physical layer design, at last, we illustrates the correct function of this design using a Xilinx KC705 evaluation board.
Keywords :
"Physical layer","Clocks","Protocols","Field programmable gate arrays","Timing","Reliability","Transforms"
Conference_Titel :
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN :
978-1-4799-8483-1
Electronic_ISBN :
2162-755X
DOI :
10.1109/ASICON.2015.7517172
