Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links

Through Silicon Vias (TSVs) based 3D Network on Chip (NoC) is a promising communication platform solution for future multicore systems. Due to the cost in terms of yield, chip area and design complexity, minimizing the number of TSVs in 3D integrated circuits has become an important design issue. In this paper, we present the circuit design of the proposed lateral asynchronous and vertical synchronous (LAVS) 3D NoC with double pumped vertical links and evaluate the area overhead, the die cost and the network performance of the scheme. Experiment shows the proposed scheme reduces overall router silicon area by 39.8%, and reduces the die cost by 20% for 3D NoC with 64 nodes each layer, and improves the ratio between performance and area by 16.8%.