A low-cost SoC implementation of AES algorithm for bio-signals

A low-cost SoC implementation of AES algorithm for bio-signals is proposed in this paper. In order to reduce signal delay, we propose three kinds of structure, namely the classic architecture, the architecture including a DMA and the architecture with the wavelet transform module and AES module integrated. As a result, the architecture with modules integrated can obtain minimum data latency and minimum area. In this design, we present a simplified 5/3 lifting wavelet processor (LWP) and a compact AES algorithm hardware accelerator (AESACR) for the purpose of reducing the area of the SoC. In SMIC 65nm CMOS process, the area of the optimal structure is 48813um² Meanwhile, the maximum throughput is 633Mbps and the maximum frequency reaches 1GHz.