Instruction-Level Instantaneous Power Modeling for VLIW Processor

Traditional instruction-level power model can evaluate the average power consumption of software, but lacks of the analysis of instantaneous power consumption. In this paper, a cycle-scale accurate power model is established for clustering VLIW structure processor from two aspects, pipeline and instruction code, which can complete instantaneous power evaluation of the processor. Through the implements of different algorithms on a processor, the results show that the model has high accuracy. This model lays a foundation for the research of software´s low power compiling.