• DocumentCode
    3782193
  • Title

    Realization of a programmable rank-order filter architecture using capacitive threshold logic gates

  • Author

    I. Hatirnaz;F.K. Gurkaynak;Y. Leblebici

  • Author_Institution
    Dept. of Electr. & Comput. Sci., Worcester Polytech. Inst., MA, USA
  • Volume
    1
  • fYear
    1999
  • Firstpage
    435
  • Abstract
    We present a new architecture to realize a fully programmable rank order filter (ROF), based on capacitive threshold logic (CTL) gates. Variants of ROFs, especially median filters, are widely used in digital signal and image/video processing and image enhancement. The CTL realization of the majority gates used in the ROF architecture allows the filter rank and the window size to be user-programmable, using a much smaller silicon area, The overall filter architecture is also simplified significantly, compared to conventional realizations of digital median filters.
  • Keywords
    "Logic gates","Digital filters","Computer architecture","Signal processing","Silicon","Image enhancement","Digital images","Boolean functions","Windows"
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1999. ISCAS ´99. Proceedings of the 1999 IEEE International Symposium on
  • Print_ISBN
    0-7803-5471-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.1999.777904
  • Filename
    777904