Refined CPLD macrocell architecture for the effective FSM implementation

We present the refined architecture of the CPLD (complex programmable logic device) macrocell. For the one-hot-encoded Moore finite state machine (FSM), the proposed architecture allows to decrease by N (where N is the number of the FSM output functions) the number of CPLD macrocells utilized for implementation of the FSM memory. In this paper, we also present the algorithm for synthesis of the one-hot-encoded Moore FSM targeted toward implementation in the proposed CPLD macrocell architecture. We present results of industrial examples of Moore FSMs, which prove the efficacy of our architecture and the algorithm for FSM synthesis. Implementation of Moore FSM in a CPLD with the proposed macrocell architecture allows to reduce the number of utilized buried CPLD macrocells by 67% on average. Similarly, the decrease of the total number of CPLD macrocells amounts to 33% on average.