A new process integration-P/sup 3/ (pre poly plug)-for giga bit DRAM era

By utilizing not only the suitable topology generated by underlying layers but also advanced processes such as poly-oxide CMP, highly selective etch, PR (photoresist) thermal flowing, etc., a giga bit level DRAM was successfully integrated with sufficient process and design margin in patterning. This paper describes the physical and electrical characteristics of the so-called pre poly plug (P/sup 3/) process, including the overall integration scheme for cells with a minimum pitch of 0.33 /spl mu/m to accomplish cell size around 0.22 /spl mu/m/sup 2/.