Realizations of a digital clock recovery in a 8 Mbit/s 4-FSK digital radio relay system

The realization of a digital clock recovery circuit (DCR) for 2 and 8 Mbit/s digital radio-relay systems (DRRS) with 4-FSK modulation is described. This circuit is realized in lattice ispLSI devices, with speeds 60 MHz and 110 MHz, which means that gate delays are near the phase increment of the digital oscillator. The highlights of this realization are: (i) reduced influence of large zero crossing jitter, due to averaging in the transition detector and (ii) work under relatively low Eb/N0 (about 10 dB). At higher bit rates, the given DCR can be used as a pre-shaper for analog PLL, for extraction of a discrete component at symbol clock frequency.