• DocumentCode
    3782623
  • Title

    The design of low power multiple-valued logic encoder and decoder circuits

  • Author

    I.M. Thoidis;D. Soudris;I. Karafyllidis;A. Thanailakis

  • Author_Institution
    VLSI Design & Testing Centre, Democritus Univ. of Thrace, Xanthi, Greece
  • Volume
    3
  • fYear
    1999
  • Firstpage
    1623
  • Abstract
    Novel multiple-valued logic (MVL) voltage-mode circuits, namely encoder and decoder circuits, using both enhancement- and depletion-mode MOSFETs, are introduced. High performance and low power dissipation, due to zero-static power consumption during their steady-state operation, characterize the proposed circuits. More specifically, considering quaternary logic, and 0.7 /spl mu/m technology, the encoder and decoder circuits are implemented and simulated by the SPICE tool. The results obtained show substantial improvements, in terms of power, speed, and transistor count, compared with existing designs.
  • Keywords
    "Logic design","Decoding","Logic circuits","MOSFETs","Voltage","Power dissipation","Energy consumption","Steady-state","Circuit simulation","SPICE"
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 1999. Proceedings of ICECS ´99. The 6th IEEE International Conference on
  • Print_ISBN
    0-7803-5682-9
  • Type

    conf

  • DOI
    10.1109/ICECS.1999.814484
  • Filename
    814484