A 12 bit current-mode folding/interpolation CMOS A/D converter with multipliers

An 12 bit 20 MS/s current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC is implemented by a 0.65 /spl mu/m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of /spl plusmn/0.51 LSB, an integral nonlinearity (INL) of /spl plusmn/1.0 LSB, the power dissipation of 280 mW with a power supply of 5 V.