• DocumentCode
    3782655
  • Title

    Architecture and performance of 3-dimensional SOI circuits

  • Author

    Rongtian Zhang;K. Roy;D.B. Janes

  • Author_Institution
    Purdue Univ., West Lafayette, IN, USA
  • fYear
    1999
  • fDate
    6/21/1905 12:00:00 AM
  • Firstpage
    44
  • Lastpage
    45
  • Abstract
    In this paper, potential three-dimensional SOI CMOS VLSI circuit structures are laid out. Chip area, layout complexities, process costs, and impact on circuit performance are compared and discussed.
  • Keywords
    "Silicon on insulator technology","Integrated circuit interconnections","Costs","Circuit optimization","Wire","Circuit synthesis","Buildings","CMOS technology","Semiconductor device measurement","Size measurement"
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 1999. Proceedings. 1999 IEEE International
  • ISSN
    1078-621X
  • Print_ISBN
    0-7803-5456-7
  • Type

    conf

  • DOI
    10.1109/SOI.1999.819850
  • Filename
    819850
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3782655