A low-power system-on-chip for telecommunications: single chip digital FM receiver/demodulator IP

A single chip digital FM receiver/demodulator system, utilizing the zero-cross detection technique, is designed and implemented as an intellectual property (IP). Zero-cross detection is performed at an IP frequency of 10.7 MHz using a sampling clock of 65536 kHz. The system is simulated for a BT=0.3 GMSK input with a data rate of 8000 bps. Simulations showed that the system has a performance comparable to those of ideal non-coherent FM demodulators. The power dissipation and area of the system are also calculated for a 0.5 /spl mu/m triple-metal standard digital CMOS process. It has been shown that the system would have a power dissipation very close to its analog counterparts when implemented with standard cells. For the case that custom flip-flop and adder cells such as ones given by Yalcin and Ismailoglu (see 1SCAS´99 Proceedings, Orlando, USA, 1999) are used, digital implementation would draw much lower current than widely available analog circuits. The silicon area occupied by the system would be in the order of 3 mm/sup 2/, making it low cost. The designed system can be used as a single IC or as an IP in a larger IC, in low-cost mobile communication applications where non-coherent detection of the transmitted signal is desired.