DocumentCode :
3782830
Title :
SiGe BiCMOS 3.3 V clock and data recovery circuits for 10 Gb/s serial transmission systems
Author :
M. Meghelli;B. Parker;H. Ainspan;M. Soyuer
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear :
2000
fDate :
6/22/1905 12:00:00 AM
Firstpage :
56
Lastpage :
57
Abstract :
A 9.95 Gb/s and a 12.5 Gb/s fully-monolithic 3.3 V clock and data recovery (CDR) circuit, are targeted at SONET OC-192 and 10GBE applications, respectively. The ICs are implemented in a production level SiGe BiCMOS with 45 GHz cut-off frequency. Compared to other technologies for high-speed ICs, such as GaAs HBT technology, SiGe BiCMOS technology has advantages. It provides a much higher integration density and enables the combination of very complex digital functions with multi-gigabit digital/analog functions on the same chip, providing cost-effective and smart solutions for complex communication systems. Several CDR circuits at 10 Gb/s using SiGe and Si technology are recently reported.
Keywords :
"Silicon germanium","Germanium silicon alloys","BiCMOS integrated circuits","Clocks","Voltage-controlled oscillators","Frequency","Delay","Detectors","Filters","SONET"
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
ISSN :
0193-6530
Print_ISBN :
0-7803-5853-8
Type :
conf
DOI :
10.1109/ISSCC.2000.839689
Filename :
839689
Link To Document :
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