Characterization of power VDMOSFETs by split C-V measurements

Split C-V measurements are evaluated as a characterization method for power VDMOSFETs. The measurement of the gate total capacitance results for VDMOSFETs in a complex curve which is superposition of the electron and hole, accumulation, depletion and inversion contributions of different interface regions. As opposed, in the split C-V measurements, giving gate-drain and gate-source capacitance, the electron and hole contributions of particular interface areas are separated. The structure of the split C-V characteristics and the gate total capacitance of a VDMOS cell is clarified. Interpretation of experimental results is confirmed by numerical 2D calculations of the split C-V characteristics by means of small signal ac analysis, and by numerical quasi-static analysis of the gate-capacitance components which originate from the different interface regions. The impact of the drain-source bias on the characteristics is explained. Applications are envisaged: measurements of technology parameters in VDMOSFETs, and separate measurement of the level of gate oxide degradation in the channel and in the epitaxial region after irradiation.