High-level power estimation with interconnect effects

We extend earlier work on high-level average power estimation to include the power due to interconnect loading. The resulting technique is a combination of an RTL-level gate count prediction method and average interconnect estimation based on Rent´s rule. The method can be adapted to be used with different place and route engines and standard cell libraries. For a number of benchmark circuits, the method is verified by extracting wire lengths from a layout of each circuit and then comparing the predicted (at RTL) power against that measured using SPICE. An average error of 14.4% is obtained for the average interconnect length, and an average error of 25.8% is obtained for average power estimation including interconnect effects.