Activity-sensitive flip-flop and latch selection for reduced energy

This article presents new techniques to evaluate the energy and delay of flip-flop and latch designs and shows that no single existing design performs well across the wide range of operating regimes present in complex systems. We prepose the use of a selection of flip-flop latch designs, each timed for different activation patterns and speed requirements. We illustrate the use of our technique on a pipelined MIPS processor datapath running SPECint95 benchmarks, where we reduce total flip-flop and latch energy by 60% without increasing cycle time.